acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 1 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 professional thin film chip resistor array the acas 0612 thin film chip resistor arrays combine the proven reliability of professional thin film chip resistor products with the advantages of chip resistor arrays. a small package enables the design of high density circuits in combination with reduction of assembly costs. four equal resistor values or tw o pairs are available. features ? advanced thin film technology ? two pairs or four equal resistor values ? tcr down to 25 ppm/k ? tolerance down to 0.5 % ? pure sn termination on ni barrier layer ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? voltage divider ? feedback circuits ? signal conditioning notes (1) resistance values to be selected from e24; e192. (2) for specified tcr tracking, tolerance matching and ev en tighter absolute tolerance and tcr please refer to da ta sheet acas 0612 - precision available on our web site at www.vishay.com/doc?28751 . technical specifications description acas 0612 eia size 0612 metric size rr1632m configuration, isolated 4 x 0603 design: all equal ae two pairs tp resistance values 47 ? to 221 k ? (1) absolute tolerance (2) ? 1 %; 0.5 % absolute temperature coefficient (2) 50 ppm/k; 25 ppm/k max. resistance ratio r min. / r max. 1:10 rated dissipation: p 70 element 0.1 w package, 4 x 0603 0.3 w operating voltage 75 v permissibe film temperature 125 c operating temperature range - 55 c to 125 c insulation voltage ( u ins ) against ambient and between isolated resistors, continuous 75 v
acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 2 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 application information the power dissipation on the resistor ge nerates a temperature rise against the local ambient, depending on the heat flow support of the printed-circuit board (therma l resistance). the rated diss ipation applies only if th e permitted film temperature is not exceeded. these resistors do not feature a limited lifetime when operated within the permissible limits. circuits notes ? products can be ordered using either th e part number or the product description. (1) r 1 = r 4 ? r 2 = r 3 . (2) please refer to the table temperature coefficient and resistance range, see next page. (3) please refer to the table packaging, see next page. design acas 0612 ae r 1 = r 2 = r 3 = r 4 tp r 1 = r 4 < r 2 = r 3 part number and product description part number: acasa110012200p500 model/ size terminal size resistance (1) accuracy grade (2) resistance (1) packaging special aca s = convex square a = 0612 3 digit resistance value r 1 , r 4 1 digit multiplier multiplier 9 = *10 -1 0 = *10 0 1 = *10 1 2 = *10 2 3 = *10 3 tcr and tolerance 1 2 3 3 digit resistance value r 2 , r 3 1 digit multiplier multiplier 9 = *10 -1 0 = *10 0 1 = *10 1 2 = *10 2 3 = *10 3 p1 p5 00 = standard product description: acas 0612 110r 1 220r p5 aca s 0612 110r 1 220r p5 model/size termination size resistance r 1 , r 4 (1) accuracy grade (2) resistance r 2 , r 3 (1) packaging aca = chip array s = convex square 0612 110r = 110 ? 1k1 = 1.1 k ? 22k1 = 22.1 k ? tcr and tolerance 1 2 3 220r = 220 ?? 1k1 = 1.1 k ? 22k1 = 22.1 k ? p1 p5 1 r 2 r 3 r 4 r aca s 0612 sa11001 2 0 c a a 20 50 p0
acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 3 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dimensions pattern styles for chip resistor array temperature coefficient and resistance range type accuracy grade absolute relative resistance value tcr tolerance tcr tolerance acas 0612 1 25 ppm/k 0.5 % - - 47 ? to 221 k ? 2 50 ppm/k 0.5 % - - 47 ? to 221 k ? 3 50 ppm/k 1 % - - 47 ? to 221 k ? packaging type code quantity packaging style width pitch reel diameter acas 0612 p1 1000 tape and reel cardboard tape acc. iec 60286-3 type i 8 mm 4 mm 180 mm/7" p5 5000 dimensions - chip resistor array, mass and relevant physical dimensions type l (mm) w (mm) h (mm) p (mm) a 1 (mm) a (mm) t 1 (mm) t 2 (mm) mass (mg) acas 0612 1.5 0.15 3.2 0.15 0.45 0.1 0.8 0.1 0.6 0.1 0.4 0.1 0.3 0.15 0.4 0.15 6.6 recommended solder pad dimensions for chip resistor arrays type g (mm) y (mm) x (mm) u (mm) z (mm) i (mm) p (mm) acas 0612 0.7 0.7 0.64 0.5 2.1 0.3 0.8 t 2 h a 1 a a t 1 w l 0.1 z g y ui x acas 0612 dimensions in mm limits for solder resist p
acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 4 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 description the production of the components is strictly controlled and follows an extensive set of instructions established for reproducibility. a homogeneou s film of metal alloy is deposited on a high grade (al 2 o 3 ) ceramic substrate using a mask to separate the adjacent resistors and conditioned to achieve the desired temperature coefficient. specially designed inner contacts are realized on both sides. a special laser is used to achieve the target value by smoothly cutting a meander groove in the resistive layer without damaging the ceramics. the resistor elements are covered by a protective coating designed for electrical, mechanical and climatic protection. the terminations receive a final pure tin on nickel plating. the result of the determined pr oduction is verified by an extensive testing procedure and optical inspection performed on 100 % of the indi vidual chip resistors. only accepted products are laid dire ctly into the paper tape in accordance with iec 60286-3 (3) . assembly the resistors are suitable for processing on automatic smd assembly systems. they ar e suitable for automatic soldering using reflow or vapour phase as shown in iec 61760-1 (3) . the encapsulation is resistant to all cleaning solvents commonly used in the electronics industry, including alcohols, esters and aqueous solutions. the suitability of conformal coatings, if applied, shall be qualified by appropriate mean s to ensure the long-term stability of the whole system. the resistors are rohs compliant; the pure tin platin g provides compatibility with lead (pb)-free and lead-contain ing soldering processes. the permitted storage time is 20 years, whereas the solderability is specified for 2 years after production or requalification. the immunity of the plating against tin whisker growth has been proven under extensive testing. all products comply with the gadsl (1) and the cefic-eeca-eicta (2) list of legal restrictions on hazardous substances. this includes full compliance with the following directives: ? 2000/53/ec end of vehicle life directive (elv) and annex ii (elv ii) ? 2011/65/ec restriction of the use of hazardous substances directive (rohs) ? 2002/96/ec waste electrical and electronic equipment directive (weee) tests where applicable, the resistors are tested in accordance with en 140401-801 which refers to en 60115-1 and en 140400 . notes (1) global automotive declarable substance list, see www.gadsl.org . (2) cefic (european chemical industry council), eeca (european electronic component manufacturers associatio n), eicta (european tra de organisation representing the information and communications technology and consumer electronics), see www.eicta.org ? policy ? environmental policy group ? chemicals ? jig ? joint industry guide (jig-101 ed 2.0). (3) the quoted iec standards are also released as en st andards with the same number and identical contents.
acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 5 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional performance 100 - 55 ambient temperature in c 155 0 rated power in % 050 70 20 40 60 80 100 125 180 derating 10k 10 resistance value r 100k 10 100 10k test voltage 100 1k v 1k 10m 1m pulse load rating for arrays with equal values, design type ae, in accordance with en 60115-1 clause 4.27; 1.2 s/50 s; 5 pulses at 12 s interval; for permissible resistance change (0.5 % r + 0.05 ) 1.2/50 pulse 10k 10 resistance value r 100k 10 100 10k test voltage 100 1k v 1k 10m 1m pulse load rating rating for arrays with equal values, design type ae in accordance with en 60115-1 clause 4.27; 10 s/700 s; 10 pulses at 1 min intervals; for permissible resistance change (0.5 % r + 0.05 ) 10/700 pulse
acas 0612 - professional www.vishay.com vishay beyschlag revision: 13-dec-12 6 document number: 28754 for technical ques tions, contact: thinfilmarray@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 tests and requirements essentially all tests are carried out in accordance with the following specifications: en 60115-1 , generic specification en 140400 , sectional specification en 140401-801 , detail specification the testing also covers most of the requirements specified by eia/is-703 and jis-c-5202. the tests are carried out in accordance with iec 60068 (1) and under standard atmospheric conditions according to iec 60068-1 (1) , 5.3. climatic category lct/uct/56 (rated temperature range: lower ca tegory temperature, upper category temperature; damp he at, long term, 56 days) is valid (lct = - 55 c/uct = 125 c). unless otherwise specified th e following values apply: temperature: 15 c to 35 c relative humidity: 45 % to 75 % air pressure: 86 kpa to 106 kpa (860 mbar to 1060 mbar) the requirements stated in the test procedures and requirements table are based on the required tests and permitted limits of en 140 401-801 where applicable. notes (1) the quoted iec standards are also released as en st andards with the same number and identical contents. (2) figures are given for arrays with equal values, design type ae. (3) for a single element. test procedures and requirements en 60115-1 clause iec 60068-2 (1) test method test procedure requirements permissible change (2) ( ? r ) stability for product types: acas 0612 47 ? to 221 k ? 4.5 - resistance - 1 %; 0.5 % 4.8.4.2 - temperature coefficient at (20/- 55/20) c and (20/125/20) c 50 ppm/k; 25 ppm/k 4.25.1 - endurance u = or u = u max.; 1.5 h on; 0.5 h off; whichever is the less severe; 70 c; 1000 h (0.25 % r + 0.05 ?? ) 4.25.3 - endurance at upper category temperature 125 c; 1000 h (0.25 % r + 0.05 ?? ) 4.24 78 (cab) damp heat, steady state (40 2) c; 56 days; (93 3) % rh (0.5 % r + 0.05 ?? ) 4.13 - short time overload (3) u = 2.5 x or u = 2 x u max. ; 5 s (0.1 % r + 0.01 ?? ) no visible damage 4.19 14 (na) rapid change of temperature 30 min at - 55 c and 30 min at 125 c; 5cycles (0.1 % r + 0.01 ?? ) no visible damage 4.18.2 58 (td) resistance to soldering heat reflow method 2 (ir/forced gas convection); (260 5) c; (10 1) s (0.25 % r + 0.01 ?? ) no visible damage 4.17.2 58 (td) solderability solder bath method; snpb; non-activated flux accelerated ageing 4 h/155 c (215 3) c; (3 0.3) s good tinning ( ? 95 % covered); no visible damage solder bath method; snagcu; non-activated flux accelerated ageing 4 h/155 c (235 3) c; (2 0.2) s 4.32 21 (ue 3 ) shear (adhesion) 45 n no visible damage 4.33 21 (ue 1 ) substrate bending depth 2 mm, 3 times (0.1 % r + 0.01 ?? ) no visible damage; no open circuit in bent position 4.7 - voltage proof u rms = u ins (60 5) s; against ambient, between adjacent resistors no flashover or breakdown p 70 x r p 70 x r
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